1. Field of Invention
The present invention relates to signal buffers, and in particular to a differential level shifting buffer.
2. Related Art
Level shifting buffers perform two functions in emitter-coupled logic (ECL) and source-coupled FET logic (SCFL) circuits. First, such buffers are used as a buffer between input and output circuits. Second, such buffers are used to shift the logic threshold voltage (the voltage defining the difference between a binary logic high or low, xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d, 1 or 0) of signals received from an input circuit to a second logic threshold voltage output to an output circuit. Such buffers frequently use a differential amplifier as an input stage, followed by a source-follower stage which performs the level shifting function. The source-follower stage may have two transistors, each of which conducts a current which passes through an impedance and a pull-down current source. The output of the buffer is taken from the nodes between the impedances and their respective pull-down current sources.
In an electrical environment with a low voltage power supply, or when the common mode potential (average potential between two differential signals) needs to be level shifted to a value near the lower supply voltage (e.g., ground) that is lower than can be sustained by a pull-down current source, these conventional circuits start to lose gain, amplitude, and bandwidth due to head room bias compression (VDS or VCE operating bias is below or near the xe2x80x9cknee voltagexe2x80x9d of the pull-down current source transistor) in the pull-down current sources.
A buffer includes two pairs of push-pull configured transistors and a compensation circuit. An input signal and its complement (e.g., the signal and complement representing a binary logic high and low, xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d, or 1 and 0, respectively) is received from, for example, a differential amplifier and voltage level shifting circuit. One transistor in the first push-pull pair receives the complement of the input signal, and one transistor in the second push-pull pair receives the input signal.
The second transistor in the first push-pull pair is coupled with a transistor in the compensation circuit to act as a first current mirror. Similarly, the second transistor in the second push-pull pair is coupled with another transistor in the compensation circuit to act as a second current mirror. Current in the first current mirror is controlled by a third transistor in the compensation circuit, and current in the second current mirror is controlled by a fourth transistor in the compensation circuit.
The signal controlling the third transistor in the compensation circuit is either the same as or is proportional to the input signal received by the first transistor in the second push-pull pair. The signal controlling the fourth transistor in the compensation circuit is either the same as or is proportional to the input signal received by the first transistor in the first push-pull pair. Thus as the first transistor in the first push-pull pair is controlled by the complement of the input signal, the second transistor in the first push-pull pair is controlled via the first current mirror by the input signal. Similarly, as the first transistor in the second push-pull pair is controlled by the input signal, the second transistor in the second push-pull pair is controlled via the second current mirror by the complement of the input signal.